/*
 * Copyright (C) 2015 MediaTek Inc.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#define U3_PHY_LIB
#include "mtk-phy.h"
#undef U3_PHY_LIB
#ifndef CONFIG_PROJECT_PHY
#error ?
#endif

#include <linuxboot/driverapi.h>
#include "mtk-phy-asic.h"

/*static struct u3phy_operator project_operators = {
        .init = phy_init_soc,
        .u2_slew_rate_calibration = u2_slew_rate_calibration,
};*/

PHY_INT32 u3phy_init(void)
{
#if  0
        if (u3phy != NULL)
                return PHY_TRUE;

        u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
        u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
        u3phy_ops = NULL;

        u3phy->u2phy_regs_e = (struct u2phy_reg_e *)U2_PHY_BASE;
        u3phy->u3phyd_regs_e = (struct u3phyd_reg_e *)U3_PHYD_BASE;
        u3phy->u3phyd_bank2_regs_e = (struct u3phyd_bank2_reg_e *)U3_PHYD_B2_BASE;
        u3phy->u3phya_regs_e = (struct u3phya_reg_e *)U3_PHYA_BASE;
        u3phy->u3phya_da_regs_e = (struct u3phya_da_reg_e *)U3_PHYA_DA_BASE;
        u3phy->sifslv_chip_regs_e = (struct sifslv_chip_reg_e *)SIFSLV_CHIP_BASE;
        u3phy->spllc_regs_e = (struct spllc_reg_e *)SIFSLV_SPLLC_BASE;
        u3phy->sifslv_fm_regs_e = (struct sifslv_fm_feg_e *)SIFSLV_FM_FEG_BASE;
        u3phy_ops = (struct u3phy_operator *)&project_operators;
#endif

        return PHY_TRUE;
}

PHY_INT32 U3PhyWriteField8(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value)
{
        PHY_INT8 cur_value;
        PHY_INT8 new_value;

        cur_value = U3PhyReadReg8((u3phy_addr_t) addr);
        new_value = (cur_value & (~mask)) | ((value << offset) & mask);

        __asm__ __volatile__("dsb":::"memory");
        U3PhyWriteReg8((u3phy_addr_t) addr, new_value);

        __asm__ __volatile__("dsb":::"memory");
        return PHY_TRUE;
}

PHY_INT32 U3PhyWriteField32(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value)
{
        PHY_INT32 cur_value;
        PHY_INT32 new_value;

        cur_value = U3PhyReadReg32((u3phy_addr_t) addr);
        new_value = (cur_value & (~mask)) | ((value << offset) & mask);

        __asm__ __volatile__("dsb":::"memory");
        U3PhyWriteReg32((u3phy_addr_t) addr, new_value);

        __asm__ __volatile__("dsb":::"memory");
        return PHY_TRUE;
}

PHY_INT32 U3PhyReadField8(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask)
{
        return (U3PhyReadReg8((u3phy_addr_t) addr) & mask) >> offset;
}

PHY_INT32 U3PhyReadField32(phys_addr_t addr, PHY_INT32 offset, PHY_INT32 mask)
{
        return (U3PhyReadReg32((u3phy_addr_t) addr) & mask) >> offset;
}

void phy_hsrx_set(void)
{
}

void phy_hsrx_reset(void)
{
}